The D-type (delay) Flip-Flop

The delay flip-flop (DFF) is unique in that it only has one external input along with a clock input. The logic symbol for this flip-flip is given below

where the two asynchronous inputs, PRESET and CLEAR enable the flip-flop to be set to a predetermined state, independent of the CLOCK. Note the invert bubble on these lines which indicates that these lines are normally held at 1 and that the function (CLEAR or PRESET) is performed by taking the line to 0.

The delay flip-flop transfers whatever is at the external input D to the output Q. This does not happen immediately however and only happens on an rising clock pulse (i.e. as CLK goes from 0 to 1). The input is thus delayed by up to a clock pulse before appearing at the output. This is illustrated in the timing diagram below. The DFF is an edge-triggered device which means that the change of state occurs on a clock transition (in this case the rising clock pulse as it goes from 0 to 1).

One implementation of the delay flip-flop is given below.

here the function of the asynchronous inputs can clearly be seen, taking PRESET momentarily to 0 sets Q=1 and taking CLEAR momentarily to 0 sets Q=0.

The delay flip-flop can also be configured from a JK flip-flop where the input connected to J and the complement of the input is connected to K.

The Delay Flip-Flop as a frequency divider

If the DFF is configured such as is indicated below then there is no external input (D has become an internal input) and only the clock pulse (CLK) is operated on. Note that for clarity the asynchronous inputs PRESET and CLEAR have been omitted from this logic diagram.

assuming the inital state of CLK=0 and Q=0 then it follows that since is connected to then D=1. As seen above then whatever is at D is transferred to Q at the next rising clock pulse so, as CLK goes from 0 to 1 Q becomes 1 and so D becomes 0. At the next rising CLK pulse the input at D (which is 0) is transferred to Q and so Q becomes 0 and hence D=1, etc. etc. This cycle is illustrated in the timing diagram below.

It can be seen that for every two clock pulses in then there is only one clock pulse out, the circuit is therefore performing division by 2.

It should be noted that this behaviour only takes places when the clock pulses are reasonably short (but at least long enough for the output to change state). If the clock pulse is long then oscillation may occur.