Ripple Counters
Both the Delay flip-flop and the JK flip-flop both enable a pulse train at the input to be divided by two. If these flip-flops as cascaded together it follows that division by 4, 8, 16, etc. can take place. In general, for n cascaded flip-flops then division by 2n is possible.
The following circuit comprises 4 JKFFs cacsaded such that the Q output from each flip-flop forms the clock input to the following flip-flop.
Note here that the invert bubbles on the clock inputs mean that the flip-flops trigger on the falling edge of each clock pulse. For all of the 4 JKFFs the J and K inputs are count enabled i.e. held at 1.
Assuming an initial state where all outputs are 0 it is possible to develop a truth table for the four outputs Qa,Qb,Qc and Qd on successive clock pulses. This is given below.
| Qd | Qc | Qb | Qa |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
| 1 | 1 | 1 | 1 |
So, on successive clock pulses the output from the four JKFFs is exactly the same as the pure binary coded representation of the decimal numbers 0 to 15. Here, Qa is weighted by 1, Qb is weighted by 2 and so on. Such a device is known as a ripple counter or a modulo-16 (mod-16) counter.
