The SR Flip-Flop
Consider a circuit comprising two NOR gates as illustrated below
here R and S are known as the external inputs, Q is known as the output or external output and Q' is known as an internal input.
Q' is called the state of the system or state variable and is related to Q, R and S via
To investigate the behaviour of the circuit we develop a truth table assuming that the feedback loop is open circuit (i.e. Q' is an external input). The corresponding truth table is then given by
| S | R | Q | Q' |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 0 |
When the feedback loop is closed this forces Q=Q'. For those instances where Q=Q' in the truth table above then nothing changes when feedback is applied and so the circuit is said to be stable. In those cases where Q and Q' are different then the application of feedback causes the inputs to change (even though R and S have remained the same) and so the circuit is said to be unstable and a new output is generated.
The circuit stability is indicated in the truth table below where S=Stable, U=Unstable and the number corresponds to a stable state number. For example S 4 means stable state 4, U 3 means this is an unstable state which, upon the application of feedback, will become stable state 3.
| S | R | Q | Q' | Stability | State |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | S | 1 |
| 0 | 0 | 1 | 1 | S | 2 |
| 0 | 1 | 0 | 0 | S | 3 |
| 0 | 1 | 1 | 0 | U | 3 |
| 1 | 0 | 0 | 1 | U | 4 |
| 1 | 0 | 1 | 1 | S | 4 |
| 1 | 1 | 0 | 0 | S | 5 |
| 1 | 1 | 1 | 0 | U | 5 |
The stability conditions are summarised in a flow table where each circled number represents a stable condition.
In general for flow tables columns are labelled with external inputs and rows are labelled with internal states.
The SR Flip-Flop as a Memory Element
Consider the following sequence of inputs applied to the circuit above
- SR=00
- stable state 1 [Q=0]
- SR=10
- switch to unstable state 4
switch to stable state 4 [Q=1] - SR=01
- switch to stable state 2 [Q=1]
- SR=01
- switch to unstable state 3
switch to stable state [Q=0]
Therefore, if S is taken to 1 (SET condition) then the output Q is set to 1. Q is subsequently held at 1 regardless of what happens to S (HOLD condition) until the input R is taken to 1 (RESET condition). When R=1 then the output Q is cleared back to 0. The condition SR=11 is prohibited for the reasons discussed below. This is the action of a SET-RESET FLIP-FLOP (SRFF) or one-bit memory element.
Problems with the SR Flip-Flop
A problem arises with the SRFF in going from SR=11 to SR=00. Ideally the circuit would switch from stable state 5 to stable state 1. In practise however S and R will not switch at the same instant.
If S switches to 0 before R then the circuit goes first to stable state 3 and then to stable state 1 where Q=0. If R switches to 0 before S however then the circuit first goes to unstable state 4 and hence to stable state 4 and then on to stable state 2 where Q=1.
Therefore the behaviour is uncertain and so the input state SR=11 must be disallowed, it is called the prohibited state.
Design of the SR Flip-Flop
The SRFF is asynchronous and operates uniquely on the input data R and S. No control data are required. The logic symbol for the SRFF looks like
In practise flip-flops usually provide two outputs i.e. Q the standard output discussed above and its complement as is illustrated above. The latter is not to be confused with the internal state variable Q'.
The SRFF can therefore be constructed either of two NOR gates plus feedback or two NAND gates plus feedback as shown in the circuit diagrams below. In the case of the NAND version it should be noted that the flip-flop is drived by the complements of S and R and so is driven by 0s rather than 1s.
